Protective coating for electrostatic chucks

ABSTRACT

An ElectroStatic Chuck (ESC) including a chucking surface having at least a portion covered with a coating of silicon oxide (SiO2), silicon nitride (Si3N4) or a combination of both. The coating can be applied in situ a processing chamber of a substrate processing tool and periodically removed and re-applied in situ to create fresh coating.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Divisional of U.S. application Ser. No.15/926,349, filed on Mar. 20, 2018, which is incorporated by referenceherein in its entirety.

BACKGROUND

ElectroStatic Chucks (ESCs) are widely used in a variety of fabricationtools, such as thin film deposition, plasma etch, photo-resist striping,substrate cleaning as well as lithography, ion implantation, etc.

ESCs operate by applying a charge of one polarity onto a chuckingsurface and a charge of the opposite polarity on a substrate. Sinceopposite charges attract, the substrate is held or clamped in place bythe resulting electrostatic force.

Coulombic and Johnsen-Rahbek (“J-R”) are two types of ESCs that arecommonly known. Both have a chucking surface that includes a dielectricformed over an electrode. With Coulombic ESCs, the dielectric is aninsulator, whereas with J-R type chucks, the dielectric has a finiteresistance (e.g., a bulk resistivity at room temperature ranging from5.0^(e+15) to 5.0^(e+16) ohm-cm and at 550 degrees C. a bulk resistivityof 5.0^(e+8) to 5.0^(e+9) ohm-cm).

SUMMARY

An ElectroStatic Chuck (ESC) is disclosed. The ESC includes a pedestalhaving a chucking surface arranged to chuck a substrate. The chuckingsurface includes at least a portion covered with a coating of eithersilicon oxide (SiO₂), silicon nitride (Si₃N₄), or a combination of both.

Also disclosed is a method of depositing a coating onto a chuckingsurface of an ESC within a processing chamber of a substrate processingtool. In non-exclusive variations of this method, the deposited coatingis either silicon oxide or silicon nitride, or a combination of both.

Further disclosed is a method for (a) using a halogen-based cleaningagent to remove a first coating formed on a chucking surface of an ESCpedestal and (b) depositing a second coating formed on the chuckingsurface of the ESC pedestal. By removing the first coating and replacingit with a second coating, the worn first coating can be refreshed with afresh second coating. In non-exclusive variations of this method, thedeposited coating is either silicon oxide or silicon nitride, or acombination of both.

In yet another embodiment, the aforementioned cleaning and coating maybe performed in situ the processing chamber. For instance, duringroutine maintenance, a halogen-based cleaning agent may be used toremove unwanted deposits and particles that have collected on surfacesinside the processing chamber as a byproduct of substrate processing.Following the cleaning, a coating of silicon oxide and/or siliconnitride is then typically applied to the clean surfaces in a subsequentplasma deposition step. Since the cleaning and recoating sequence forthe chucking surface of the ESC and the processing chamber areessentially the same, the chucking surface can be cleaned and recoatedin situ the processing chamber at the same time as the processingchamber.

The use of silicon oxide and silicon nitride formed on the chuckingsurface of an ESC has a number of advantages. The coating can be used toprotect the chucking surface from degradation and wear due to the shearlateral forces caused by different rates of thermal expansion betweensubstrates and the chucking surface. The coating of silicon oxide andsilicon nitride can be readily deposited and removed on the chuckingsurface in situ a processing chamber. As a result, an old worn coatingcan be removed and replaced with a new coating as needed or at fixedintervals, all inside the processing chamber.

In yet other non-exclusive embodiments, the coating applied to an ESCchuck can be either silicon oxide, silicon nitride, a combination ofboth silicon oxide and silicon nitride, or a multi-layer structureincluding one or more layers each of silicon oxide and silicon nitride.

BRIEF DESCRIPTION OF THE DRAWINGS

The present application and the advantages thereof, may best beunderstood by reference to the following description taken inconjunction with the accompanying drawings in which:

FIG. 1 is a block diagram of a substrate fabrication tool for processinga substrate in accordance with a non-exclusive embodiment.

FIG. 2 is a perspective view of a cross-section of an electrostaticpedestal in accordance with a non-exclusive embodiment.

FIG. 3 a flow diagram illustrating steps for periodically applying insitu a coating to the chucking surface of an ESC within a processingchamber in accordance with a non-exclusive embodiment.

FIGS. 4A and 4B are enlarged, cross-sectional views of a substrate withdifferent protective coatings in accordance with non-exclusiveembodiments.

FIG. 5 is a block diagram of a computing system that may be configuredas a controller for controlling the substrate fabrication tool inaccordance with a non-exclusive embodiment.

In the drawings, like reference numerals are sometimes used to designatelike structural elements. It should also be appreciated that thedepictions in the figures are diagrammatic and not necessarily to scale.

DETAILED DESCRIPTION

The present application will now be described in detail with referenceto a few non-exclusive embodiments thereof as illustrated in theaccompanying drawings. In the following description, numerous specificdetails are set forth in order to provide a thorough understanding ofthe present disclosure. It will be apparent, however, to one skilled inthe art, that the present discloser may be practiced without some or allof these specific details. In other instances, well known process stepsand/or structures have not been described in detail in order to notunnecessarily obscure the present disclosure.

ESCs, regardless of type, have several limitations. Fluorine is oftenused during the deposition of substrates, such as semiconductor wafers.The exposure of the clamping surface of an ESC to fluorine can introducecharge traps in the dielectric, negatively affecting its electricalproperties, reducing the ability to clamp with sufficient force. Also,residual carbon, a by-product of many CVD processes, can also form onthe clamping surface. Since carbon is an insulator, its presence on theclamping surface may interfere with the J-R type ESCs, also diminishingclamping strength.

It is known to use a Protective Electrostatic Cover (PEC) over theclamping surface of an ESC to prevent exposure to fluorine and/orresidual carbon. The use of a PEC, however, creates a number ofcomplications. A storage location within or adjacent the processingchamber is needed when the PEC is not in use. In addition, a mechanismis needed to move and position the PEC between its storage location andthe ESC substrate. Such mechanisms tend to generate unwanted particles,require periodic maintenance, and often break. In addition, controlsoftware is needed to control the operation of the mechanism. Suchcontrol software tends to add complexity to the tool and increasedevelopment costs.

FIG. 1 is a block diagram of a substrate processing tool 100 that may beused in a non-exclusive embodiment. The substrate processing tool 100,in this example, includes a processing chamber 102, a gas source 104, aRadio Frequency (RF) source 106, a bias source 108, an exhaust pump 110,a temperature controller 112, vacuum source 114 and a controller 116.The processing chamber 102 includes an electrode 118, coupled to the RFsource 106, and an ElectroStatic Chuck (ESC) pedestal 120 for chucking asubstrate 122.

During operation of the tool 100, a substrate 122 is chucked onto theESC pedestal 120 within the processing chamber 102 containing a gassupplied by gas source 104. When RF power from RF source 106 is appliedto electrode 118, a plasma for processing the substrate 122 within theprocessing chamber 102 is created. Depending on the type of tool, theplasma may be used to process the substrate 122 in a number of ways,including thin film deposition, etching, etc.

Although not illustrated, it should be noted that in alternativeembodiments, the RF source 106 can be alternatively coupled to thepedestal 120. With this alternative embodiment, the pedestal 120 alsoacts as the electrode for generating the plasma within the processingchamber 102.

Also during operation, the controller 116 may selectively control anumber of operations within the processing chamber 102, such as the biasapplied to the substrate 122 via the bias source 108, the exhausting ofthe plasma or other gases out of the processing chamber 102 via theexhaust pump 110, the temperature of the pedestal 120 and/or thesubstrate 122 via the temperature controller 112 and the vacuum source114. As each of these elements and their operation are well known, adetailed explanation is not provided herein for the sake of brevity.

In FIG. 1 , the various electrical and/or tubing are provided betweenthe various components 108 through 116 and processing chamber 102 and/orthe pedestal 120. It should be noted that, for the sake of notover-complicating the details of the drawing, the various electricaland/or tubing connections as illustrated is simplified as a singleconnection 124. It is well understood that routing of the variouselectrical and tubing in and out of the processing chamber 102 and/or tothe pedestal 120 is very complex, but is not addressed herein for thesake of brevity.

In one non-exclusive embodiment, tool 100 may include or operate incooperation with a remote plasma source 126. A plasma generated in theremote plasma source 126 is supplied to the processing chamber 102. Onepossible reason to use a remote plasma generator is to reduce oreliminate the ion bombardment of surfaces within the processing chamber102, which is typically undesired. For instance, in a non-exclusiveembodiment, the remote plasma source 126 may be used for cleaning theprocessing chamber 102, which tends to increase the longevity of varioussurfaces and/or components within the processing chamber 102 by reducingtheir exposure ion bombardment, which typically accelerates degradation.

In alternative embodiments, the pedestal 120 is either a Coulombic andJohnsen-Rahbek (“J-R”) type ESC.

In yet other embodiments, the pedestal 120 may be made of a number ofthermally conductive materials. Such materials may include, but are notlimited to aluminum nitride, aluminum oxide, ceramic, other thermallyconductive materials, or any combination thereof.

The tool 100 can be one of several different types of Chemical VaporDeposition (CVD) tools, such as a Low Pressure CVD (LPCVD), Ultra HighVacuum CVS (UHVCVD), a Plasma Enhanced CVD (PECVD), a Remote PlasmaEnhanced CVD (RPECVD) or an Atomic Layer Deposition (ALDCVD). As each ofthese tools is well known, a detailed explanation is not provided hereinfor the sake of brevity. However, regardless of the type of CVD tool,the substrate 122 is typically exposed to one or more precursors, whichreact or decompose on the surface of the substrate 122, forming adesired deposition layer. By repeating this process multiple times,multiple layers can be formed on the surface of the substrate 122. Itshould be understood that this list of CVD tools provided herein is notexhaustive and should not be construed as limiting. On the contrary, thepedestal 120 as described herein may be used with any type of CVD toolor tool that is used to process a substrate.

Referring to FIG. 2 , a perspective, cross-sectional diagram of the ESCpedestal 120 is shown. The ESC pedestal 120 includes an ESC chuck 202having a chucking surface 204 for chucking a substrate (not shown), apedestal stem 206 that is arranged to support the ESC chuck 202 whenmounted onto a recess provided in a pedestal mount 208.

The chucking surface 204 includes a plurality of raised Minimum ContactAreas (MCAs) 210. In a non-exclusive embodiment, the ESC chuck 202,chucking surface 204 and MCAs are made of aluminum nitride. At theoperating temperatures (e.g., 400 to 650 degrees C.) commonly used in aCVD processing chamber, such as processing chamber 102, aluminum nitridehas a finite resistance. As such, ESC pedestal 120 in this particularembodiment is a JR type ESC. In other embodiments, other materials maybe used. With materials that are electric insulators, the ESC pedestalwould be a Coulombic type ESC.

The MCAs 210 perform a number of functions. First, the MCAs 210 definethe surface area in physical contact with the backside of the substrate122 when chucked on surface 204. As a result, the charge transferrequired to generate the clamping electrostatic force is concentrated inthese locations. Second, the MCAs 210 reduce the amount of surface areaof the backside of a substrate 122 in contact with the chucking surface204. As a result, both metal contamination and current leakage isreduced.

In one particular embodiment, the MCAs 210 are round in shape, have aheight of approximately 1 mill (0.001 of an inch), a diameter ofapproximately 0.028 of an inch (0.7112 millimeters) and a pitch of 0.015inches (3.81 millimeters). It should be pointed out that FIG. 2 is notdrawn to scale. For the sake of clarity, the MCAs 210 as shown aresignificantly larger relative to the chucking surface 204. In actualembodiments, the MCAs 210 would typically be smaller than illustrated.

The FIG. 2 embodiment is merely exemplary and should not be construed aslimiting. In various other embodiments, the MCAs 210 may assume variousshapes (e.g., square, rectangular, oval, polygon, etc.), may have aheight taller or shorter, may vary in dimensions and pitch, and maycover a larger or smaller percentage of the chucking surface 204. Inaddition, the MCAs 210 may be arranged in a wide variety of arrangements(e.g., rows, columns, a specific pattern, etc.) on the chucking surface204. In actual embodiments, the shape, height, pitch, surface area andpattern on the chucking surface 204 may widely vary and is at leastpartially dictated by a number of design constraints, such as the sizeof the substrate 122, the amount of clamping force needed, the type oftool 100, and a host of other engineering considerations.

The MCAs 210 and the substrate 122, such as a silicon wafer, aretypically made of different materials. As a result, MCAs 210 and thebackside of the substrate 122 will typically expand/contract atdifferent rates with temperature changes incurred during clamping withinthe processing chamber 102. The different expansion/contraction ratescreate shear lateral forces across the top surfaces of the MCAs 210.Over time, these forces have been known to degrade the MCAs 210,changing surface roughness, reducing height, and altering theirelectrical properties, all of which tend to degrade the degree ofelectrostatic force generated at the chucking surface 204.

Conventional practice dictates that no material be deposited on thechucking surface 204 and/or MCAs 210 of an ESC 120. If such a materialis present, charge traps will normally occur at or near the chuckingsurface, adversely affecting its electrical properties and interferingwith the electrostatic charge clamping effect. Therefore, as a generalrule, no material or coating is typically applied to or otherwiseprovided on the clamping surface with conventional ESCs.

Contrary to conventional practice, the Applicant proposes of siliconoxide (SiO₂) or silicon nitride (Si₃N₄) as a coating on the chuckingsurface 204 of the ESC 120. Electrons in both silicon oxide and siliconnitride become more excited at elevated temperatures. As a result,either of these materials (or a combination of both) becomes moreconductive, and tends to act more like dielectric with finiteresistance, at elevated temperatures in the range of 450 to 600 degreesC. Since this temperature range is often used in certain processingchamber of substrate processing tools, such as CVD tools, the Applicanthas discovered that silicon oxide and/or silicon nitride can in fact beadvantageously used on the chucking surface of an ESC.

The use of silicon oxide and silicon nitride formed on the chuckingsurface 204, including the MCAs 210, has a number of advantages:

(1) The coating can be used to protect the MCAs 210 from degradation andwear due to the shear lateral forces caused by different rates ofthermal expansion of substrates 122 as noted above;

(2) The coating of silicon oxide and silicon nitride can be readilydeposited and removed on the chucking surface 204 and/or MCAs 210 insitu the processing chamber 102. As a result, an old worn coating can beremoved and replaced with a new coating as needed or at fixed intervals,all inside the processing chamber 102; and

(3) Furthermore, the particle performance of processing chamber 102 canbe improved by applying a coating onto the surfaces of the pedestal 120and processing chamber 102. This coating adheres particles to thesessurfaces of, reducing the likelihood of particle contamination on thesubstrate 122. The coating additionally provides a protective layer forany metal contamination on the chucking surface 204 of the pedestal 120,thereby minimizing metal contamination being transferred onto thesubstrates.

Referring to FIG. 3 , a flow diagram 300 illustrating steps forperiodically applying a coating to the chucking surface 204 of an ESC120 in situ a processing chamber 102 is shown.

In the initial step 302, a coating of either silicon oxide or siliconnitride (or a combination of the two) is formed at least partially,including on the MCAs 210, of the chucking surface 204 of an ESC chuck202. The coating is formed by introducing a silicon precursor and areactant into the processing chamber 102. A chemical vapor deposition(CVD) plasma is then generated while the silicon precursor and thereactant are in the processing chamber. As a result, a coating isdeposited or formed on the chucking surface 204.

In one embodiment, the coating is formed across the entire chuckingsurface 204, including the MCAs 210. In other embodiments, portions ofthe chucking surface 204 can be masked and the mask later removed afterthe coating is formed. As a result, the coating is provided only on thenon-masked portions of the chucking surface 204.

In various embodiments, the silicon precursor or silicon source isselected from the group including (a) silane, (b) TetraethylOrthosilicate (TEOS), or a combination of both (a) and (b). The reactantis selected from the group including (a) oxygen (O₂), (b) nitrous oxide(N₂O), (c) ammonia (NH3), (d) nitrogen (N2) or any combination of (a)through (c). Once the precursor and the reactant are present in theprocessing chamber 102, the coating can be deposited during a CVDprocess.

The material make-up of the coating depends on the type of reactantused. With either silane or TEOS as a precursor, a silicon coating isgrown or deposited on the chucking surface 204. If the reactant is anoxidizer, such as either oxygen or nitrous oxide, then the siliconcoating is oxidized, resulting in silicon oxide. On the other hand ifthe reactant is ammonia or nitrogen, then silicon nitride results.

If both ammonia and oxygen and/or nitrous oxide is used as the reactant,then the resulting coating is a mix of both Silicon oxide and Siliconnitride.

Alternatively, by using one reactant initially and then later the otherreactant, a multi-layered coating can be formed. For instance, byinitially using oxygen and/or nitrous oxide and later ammonia, amulti-layered coating is formed with silicon oxide on the bottom andsilicon nitride on the top. By swapping the sequence of the reactants, acomplementary multi-layered structure can be created.

In step 304, substrates 122 are loaded into substrate processing tool100 once the coating of desired material and thickness is formed inprior steps.

In step 306, the substrates 122 are processed in the processing chamber102. The processing generally involves chucking a substrate 122 onto thechucking surface 204 of the ESC 120 and maintaining a temperature withinthe processing chamber within a predetermined range. As noted above,this range may be 400 to 650 degrees C. in one embodiment. In otherembodiments, other ranges with higher or lower temperatures may be used.Once chucked, the substrate 122 is processed within the processingchamber 102. As noted above, the processing may involve thin film layerdeposition, etching, photo-resist striping, substrate cleaning as wellas lithography, ion implantation, etc.

In step 308, a decision is made if the processing chamber 102 needs tobe cleaned or not. A number of factors may be used in making thisdecision. The decision can be based on an accumulated amount ofprocesses conducted within the processing chamber 102 over a period oftime. If the tool 102 is a CVD tool for instance, then cleaningintervals may be determined based on a specified amount of depositionmaterial having been deposited on substrates 122 since the priorcleaning. Other decision factors may include time (e.g., the tool iscleaned at a periodic fixed interval) or after a predetermined number ofsubstrates 122 have been processed, or any combination of these or otherfactors. If a decision is made to not clean the processing chamber 102,then steps 304 and/or 306 are repeated.

If a decision is made that it is time to clean the processing chamber102, then a cleaning operation within the processing chamber 102,including the chucking surface 204, is performed as provided in step310. The cleaning process generally involves using a halogen-basedcleaning agent to remove the coating formed on a chucking surface 204 ofthe ESC 120 in situ within the processing chamber 102. A halogen-basedcleaning agent, such as fluorine, nitrogen trifluoride or other fluorinecontains gases, is introduced into the processing chamber 102. A plasmais then generated, which removes or etches away the coating on thechucking surface 204 and MCAs 210 along with other exposed surfaces, asis well known in the art.

Once the coating is removed, a new coating is formed on the chuckingsurface 204 and MCAs 210 as provided above in steps 302. Thereafter,steps 304 through 310 can be repeated over and over. With each cycle, anold, worn coating is removed in step 310 and a new, fresh coating isapplied in step 302.

In yet another embodiment, the aforementioned cleaning and coating maybe performed in situ the substrate processing tool during routinemaintenance of the processing chamber 102. For instance, a halogen-basedcleaning agent may be used from time-to-time to remove unwanted depositsand particles that have collected on surfaces inside the processingchamber 102 as a byproduct of substrate processing. Following thecleaning, a coating of silicon oxide and/or silicon nitride is thentypically deposited to the clean surfaces within the processing chamber102 in a subsequent plasma deposition step. Since the cleaning andrecoating sequence for the chucking surface 204 of the pedestal 120 andthe processing chamber 102 are essentially the same, both can be cleanedand recoated in situ the processing chamber 120 using the same cleaningand deposition sequence.

Referring to FIG. 4A, an enlarged, cross-sectional view of a substrate122 on the chucking surface 204 of an ESC chuck 202 is shown. With thisembodiment, a coating 402 is provided over and between the MCAs 210,covering the entire chucking surface 204. As previously noted, thecoating 402 can be silicon oxide, silicon nitride or a combination ofboth.

Referring to FIG. 4B, another enlarged, cross-sectional view of asubstrate 122 on the chucking surface 204 of an ESC chuck 202 is shown.With this embodiment, multi-layer coating 404 is provided over andbetween the MCAs, including top layer 406 and bottom layer 408. Aspreviously noted, the top layer 406 can be silicon oxide and the bottomlayer 408 silicon nitride or vice-versa.

Although the two embodiments of FIG. 4A and FIG. 4B show the coating402/404 over the entire chucking surface 204 including MCAs 210, thesediagrams as depicted should not be limiting. On the contrary, thecoatings 402/404 can be only partially formed on the chucking surface204, for instance, just on the top of the MCAs 210.

In yet other embodiments, the coating, regardless of whether it is asingle layer (e.g., FIG. 4A) or multi-layer (e.g., FIG. 4B), isapproximately 2.5 microns thick. In alternative embodiments, the coatingmay range in thickness from 1.0 to 5.0 microns or from 50 nanometers to30 microns. With thicker coatings, such as 1.0 or more, withconventional CVD tools, thicker coating in the 1.0 to 5.0 micron rangeare typically applied. With other tools such as Atomic Layer Deposition(ALDCVD) tools, extremely thin coating of approximately 50 nanometerscan be applied.

With certain substrate processing tools 100 that include or operate incooperation with a remote plasma source 126 (as shown in FIG. 1 ), thevarious plasma used to either form or remove the coating(s) 402/404, asdescribed above with regard to steps 302 and 310, can be generatedremotely in remote plasma source 126 and then supplied into theprocessing chamber 102 including the ESC 120. The above-described stepsof removing old coating and replacing with a fresh coating is otherwisemore less the same as described above.

Silicon oxide and silicon nitride (or a combination of both) can be usedon the chucking surface 204, at elevated temperatures, without adverselyaffecting the electrostatic forces needed to clamp a substrate 122.While a specific range is noted above, it should be understood thatthese temperatures should not be construed as limiting. On the contrary,any temperature may apply, provided the electrical conductivity of thesilicon oxide or silicon nitride is increased to the level where the atleast a portion of the chucking surface 204 coated with the Siliconoxide or Silicon nitride generates a sufficient electrostatic force toclamp the substrate.

The coating 402/404 also helps improve substrate clamping by solving anumber of issues that plaque conventional electrostatic substratechucks. For instance, the presence of carbon on a chucking surface of anelectrostatic chuck is known to possibly cause electrical shorting,which tends to reduce the electrostatic clamping force between thechucking surface and the substrate. The above-described coating process,however, tends to remove the presence of carbon from the chuckingsurface. As a result, the incidence of electrical shorting issignificantly reduced. In addition, the presence of fluorine within aprocessing chamber is known to penetrate certain types of chuckingsurfaces, such as those made of ceramic, creating charge-traps. However,the Applicant has found that at the processing temperatures of 450 to600 degrees C. as described herein, the incidence of charge-traps isreduced. As a result, the electrostatic clamping force is not adverselyaffected.

Referring to FIG. 5 , a block diagram of a computing system that may beconfigured as the controller 116 for controlling the substrateprocessing tool 100 in accordance with a non-exclusive embodiment isshown.

The controller 116 may have many physical forms ranging from a computer,server, a small handheld device up to a huge super computer. Thecontroller 116 includes one or more processors 502, and further caninclude an electronic display device 504 (for displaying graphics, text,and other data), a main memory 506 (e.g., random access memory (RAM)),storage device 508 (e.g., hard disk drive), removable storage device 510(e.g., optical disk drive), user interface devices 512 (e.g., keyboards,touch screens, keypads, mice or other pointing devices, etc.), and acommunication interface 514 (e.g., wireless network interface). Thecommunication interface 514 allows software and data to be transferredbetween the controller 116 and external devices via a link. Thecontroller 116 may also include a communications infrastructure 516(e.g., a communications bus, cross-over bar, or network) to which theaforementioned devices/modules are connected.

Information transferred via communications interface 514 may be in theform of signals such as electronic, electromagnetic, optical, or othersignals capable of being received by communications interface 514, via acommunication link that carries signals and may be implemented usingwire or cable, fiber optics, a phone line, a cellular phone link, aradio frequency link, and/or other communication channels. With such acommunications interface, it is contemplated that the one or moreprocessors 502 might receive information from a network, or might outputinformation to the network in the course of performing theabove-described method steps. Furthermore, method embodiments mayexecute solely upon the processors or may execute over a network such asthe Internet, in conjunction with remote processors that share a portionof the processing.

The term “non-transient computer readable medium” is used generally torefer to media such as main memory, secondary memory, removable storage,and storage devices, such as hard disks, flash memory, disk drivememory, CD-ROM and other forms of persistent memory and shall not beconstrued to cover transitory subject matter, such as carrier waves orsignals. Examples of computer code include machine code, such asproduced by a compiler, and files containing higher level code that areexecuted by a computer using an interpreter. Computer readable media mayalso be computer code transmitted by a computer data signal embodied ina carrier wave and representing a sequence of instructions that areexecutable by a processor.

It should be understood that while the present application is describedin the context of various deposition tools, by no means this beconstrued as limiting. On the contrary the ESC pedestal 120 as describedherein may be used in a wide variety of substrate processing tools,including but not limited to, lithography tools, plasma etching orchemical etching tools, ion implantation tools, substrate cleaningtools, etc.

Although only a few embodiments have been described in detail, it shouldbe appreciated that the present application may be implemented in manyother forms without departing from the spirit or scope of the disclosureprovided herein. For instance, the substrate can be a semiconductorwafer, a discrete semiconductor device, a flat panel display, or anyother type of work piece.

Therefore, the present embodiments should be considered illustrative andnot restrictive and is not to be limited to the details given herein,but may be modified within the scope and equivalents of the appendedclaims.

What is claimed is:
 1. An ElectroStatic Chuck (ESC), comprising apedestal having a chucking surface arranged to chuck a substrate,wherein the electrostatic chuck is configured to generate electrostaticforce at the chucking surface to clamp the substrate, wherein thechucking surface has a multi-layered coating comprising a top layer ofsilicon oxide and a bottom layer of silicon nitride or vice versa,wherein a material of an entirety or substantial entirety of the toplayer is different from a material of an entirety or substantialentirety of the bottom layer, and wherein the multi-layered coatingreduces charge traps in the chucking surface, wherein the multi-layeredcoating has a thickness ranging from 50 nanometers to 30 microns,wherein the ESC is further arranged to operate within a substrateprocessing chamber maintained at an elevated temperature such that anelectrical conductivity of the silicon oxide or silicon nitride isincreased to a level where the chucking surface generates sufficientelectrostatic force to clamp the substrate.
 2. The ESC of claim 1,wherein the multi-layered coating comprises the top layer of siliconoxide and the bottom layer of silicon nitride.
 3. The ESC of claim 1,wherein the multi-layered coating comprises the top layer of siliconnitride and the bottom layer of silicon oxide.
 4. The ESC of claim 1,wherein the chucking surface on which the multi-layered coating isformed comprises a dielectric over an electrode.
 5. The ESC of claim 1,further arranged to operate, when the substrate is chucked to thechucking surface within a substrate processing chamber, at a temperatureranging from 450 to 600 degrees C.
 6. The ESC of claim 1, wherein thechucking surface with the coating of the silicon oxide or the siliconnitride includes one or more minimum contact areas formed on thechucking surface.
 7. The ESC of claim 1, wherein the ESC is either aCoulombic type ESC or a Johnsen-Rahbek (J-R) type ESC.